1. Field of the Invention
The present invention relates to a flat panel display and, more particularly, to a flat panel display including a driving circuit in which a timing controller and a data driver for driving a panel are mounted on a single integrated circuit (IC), and a driving circuit thereof.
2. Description of the Related Art
A flat panel display (FPD) is a display device essential to implementing a compact and lightweight system such as portable computers, notebook computers, personal digital assistants (PDAs), or portable phone terminals, as well as monitors of desktop computers in the place of the conventional cathode ray tubes (CRTs). Currently commercialized flat panel displays include a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED), and the like.
With reference to FIG. 1, an FPD generally has a structure including a timing controller receiving various signals from an external system 1 and generating control signals of a driver, gate and data drivers 6 and 7 generating a scan signal and an image signal corresponding to the signal generated by the timing controller 3, and a display panel 9 including gate lines GL and data lines DL disposed in a matrix form, receiving scan signals and image signals to control switching elements T to implement an image.
According to a high integration trend of an integrated circuit (IC), among driving circuits provided in the FPD having such a structure, a multiple drive IC (M-IC) in which the timing controller 3 and the data driver 7 are installed in a single IC has been proposed. FIG. 2 is a view illustrating a structure of an FPD including an M-IC.
With reference to FIG. 2, a plurality of M-ICs 3 are mounted on a printed circuit board (PCB), connected to an external system 1 to receive timing signals and an image signal, and connected to a gate driver 6 and a display panel 9 to generate control signals and to transmit processed and converted image signal.
As described above, the M-IC 3 is formed by installing an existing timing controller (3 in FIG. 1) and the data driver (7 in FIG. 1) in a single IC. A plurality of M-ICs 3a, 3b, and 3c are provided and each of the M-ICs 3a, 3b, and 3c has the same internal structure. An internal structure of the M-IC 3a will be described as an example. The M-IC 3a includes a clock generating unit 31a generating an internal clock signal of an IC itself, a synchronization signal generating unit 32a generating a synchronization signal when driving in fail-safe mode, a mode selector unit 33a for determining a driving mode according to a signal received from the external system 1, a signal processing unit 35a for timing signals and for processing and converting an image signal according to a determination of the mode selector unit 32, and a D-IC unit 37a for performing the same function as that of the existing data driver 7.
The FPD employing the M-IC 3 having such a structure is advantageous in that the number of provided ICs can be reduced and production costs can be reduced by simplifying the internal structure.
However, the FPD employing the M-IC 3 disadvantageously has a high possibility that no-signal driving of displaying a black screen on a screen is not smoothly performed when a signal is not received from the external system 1.
In detail, in the FPD employing the M-IC 3, all of the M-ICs 3a, 3b, and 3c are synchronized to be operated by timing signals applied from the external system 1, and if any one of a plurality of signals is not received from the external system 1, the respective M-ICs 3a, 3b, and 3c are changed to a fail-safe mode.
The fail-safe mode refers to a mode where the M-ICs 3a, 3b, and 3c operate to display a black screen by using an internal clock signal because a synchronization signal is not received. Since controls signal are not applied by the external system 1 in the fail-safe mode, the M-ICs 3a, 3b, and 3c are not synchronized, so they generates a synchronization signal by using an internal clock signal and display a black screen image (or blue screen image) according to the generated synchronization signal
Here, the respective clock generation units 31a, 31b, and 31c included in the M-ICs 3a, 3b, and 3c have significant variations therebetween, and thus, frequencies of the synchronization signals generated by the respective M-ICs 3a, 3b, and 3c are not identical, failing to properly perform synchronization. Thus, in order to solve the synchronization problem, any one (M-IC 3a) of the respective M-ICs 3a, 3b, and 3c are set as a master and the other remaining M-ICs 3b and 3c are set as slaves. When they are driven in the fail-safe mode, a synchronization signal generated by the internal clock signal of the master M-IC 3a is shared to operate the mode selector units 32b and 32c of the slaves, as well as the mode selector unit 32a of the master to synchronize the respective M-ICs 3a, 3b, and 3c. A block image signal corresponding to a black screen is generated and output to D-IC units 37a, 37b, and 37c. 
However, the M-ICs 3a, 3b, and 3c are mounted on a general PCB and share the synchronization signal of the master M-IC 3a through a line (PLINE) formed on the PCB. Thus, the M-ICs 3a, 3b, and 3c are affected by electrostatic discharge (ESD) or external noise, frequently causing the synchronization signal to be modulated.
Thus, in case of the fail-safe mode driving, the M-ICs malfunction, so the FPD having the related art M-ICs cannot display a black screen image.